Meta-Computer (Verbose)[ Home ] [ Previous ] [ Next ]{ Σπ } In order to initialize all of the 3D lattices of wires and logic gates, a meta-computer is required. The program code of this meta-computer (concise form) fits into 64 bits. The input of the meta-computer is the set of all integers up to 2 ^ 65,536 bits long. The output of the meta-computer is the set of all possible configurations of 3D lattices. The dimensions of each lattice are (2 ^ 16) x (2 ^ 16) x (2 ^ 65,501). The following is the program code of this meta-computer, in the form of high-level language code. First some programming notes: X := Y is an assignment statement, in which the value of Y is stored in the variable X; IF X <> 0 means IF X is not equal to zero. Let M = an integer with 2 ^ 65,536 bits Let X, Y = integers with 16 bits each Let Z = an integer with 65,501 bits Let I = an integer with 65,533 bits Let V = an integer with 8 bits Let L(X, Y, Z) = a grid intersection in lattice L, consisting of 6 bits Let M(I) = I-th byte of M (a byte has 8 bits) Let L(I) = I-th grid intersection of lattice L (3D array) M := 0 20 I := 0 Z := 0 40 Y := 0 60 X := 0 80 V := M(I) L(X, Y, Z) := V I := I + 1 X := X + 1 IF X <> 0 GOTO 80 Y := Y + 1 IF Y <> 0 GOTO 60 Z := Z + 1 IF I <> 0 GOTO 40 ACTIVATE L M := M + 1 IF M <> 0 GOTO 20 HALT Here is the program code of the meta-computer, in the form of an assembly language program, beginning with its instruction set (the Siz column is the instruction length, in multiples of 4 bits):
Instruction Set:
Siz Op Args Function
=== === ==== ========
4 LD V, M, I Load V := M(I) = I-th byte of M
5 STO X, Y, Z, V Store L(X, Y, Z) := V
4 ACC X, Val Reserve up to 255 bits for register X
2 EXP X Reserve 2 ^ Y bits for register X,
where Y is the current length of X
2 SHR X Shrink length of register X by 1 bit
2 CLR X Zero out X
2 INC X Increment X
4 BNZ X, Val Branch if X non-zero
1 RUN Activate current lattice, start new lattice
1 HLT Halt
Assembly Language Program (Hexadecimal):
00 ACC M, 10 30 LD V, M, I
04 EXP M 34 STO X, Y, Z, V
06 EXP M 39 INC I
08 ACC X, 10 3B INC X
0C ACC Y, 10 3D BNZ X, 30
10 ACC I, 10 41 INC Y
14 EXP I 43 BNZ Y, 2E
16 SHR I 47 INC Z
18 SHR I 49 BNZ I, 2C
1A SHR I 4D RUN
1C ACC Z, 10 4E INC M
20 EXP Z 50 BNZ M, 28
22 ACC V, 8 54 HLT
26 CLR M
28 CLR I
2A CLR Z
2C CLR Y
2E CLR X
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